Please keep at least one language enabled. || కనీసం ఒక భాషను ఎంచుకోండి.
Question 1
ప్రశ్న 1
A processor contains L1, L2 and L3 cache memories. Which cache level is generally positioned closest to the CPU execution core and provides the lowest access time?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• L1 cache is normally the cache level closest to the processor core and is designed for extremely fast access.
• L2 is generally larger but somewhat slower than L1, while L3 is usually still larger and slower than L1/L2.
• Main memory lies below the cache hierarchy and has a considerably higher access time.
• L2 is generally larger but somewhat slower than L1, while L3 is usually still larger and slower than L1/L2.
• Main memory lies below the cache hierarchy and has a considerably higher access time.
వివరణ:
Question 2
ప్రశ్న 2
During instruction execution, which CPU register normally contains the address of the next instruction to be fetched?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• The Program Counter holds the address of the instruction that is to be fetched next.
• After an instruction fetch, its value is normally updated so that execution can proceed through the program sequence.
• The Instruction Register instead holds the instruction currently being decoded or executed.
• After an instruction fetch, its value is normally updated so that execution can proceed through the program sequence.
• The Instruction Register instead holds the instruction currently being decoded or executed.
వివరణ:
Question 3
ప్రశ్న 3
Which CPU register normally holds the instruction that has just been fetched and is currently being decoded or executed?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• The Instruction Register holds the currently fetched instruction while the processor decodes and executes it.
• The Program Counter identifies the address of the next instruction rather than holding the current instruction itself.
• Address and data transfer registers serve different roles in communication with memory.
• The Program Counter identifies the address of the next instruction rather than holding the current instruction itself.
• Address and data transfer registers serve different roles in communication with memory.
వివరణ:
Question 4
ప్రశ్న 4
The CPU requests a data item and finds a valid copy of that item in cache memory. This event is called a:
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• A cache hit occurs when the information requested by the processor is already available in the cache.
• The processor can then obtain the item without waiting for a slower access to main memory.
• A cache miss occurs when the required information is not present in the relevant cache.
• The processor can then obtain the item without waiting for a slower access to main memory.
• A cache miss occurs when the required information is not present in the relevant cache.
వివరణ:
Question 5
ప్రశ్న 5
When the processor searches the cache for required information but the information is not present, what normally happens next?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Failure to find required information in cache is called a cache miss.
• The system then accesses a lower memory level, such as another cache level or main memory, to obtain the requested information.
• This additional access contributes to the performance cost known as the miss penalty.
• The system then accesses a lower memory level, such as another cache level or main memory, to obtain the requested information.
• This additional access contributes to the performance cost known as the miss penalty.
వివరణ:
Question 6
ప్రశ్న 6
Which statement most accurately describes the general relationship among L1, L2 and L3 cache levels in a modern processor?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• L1 prioritizes very low access time and therefore normally has relatively small capacity.
• L2 and L3 generally provide progressively greater capacity while sacrificing some speed compared with L1.
• All three are high-speed cache levels and are fundamentally different from secondary storage.
• L2 and L3 generally provide progressively greater capacity while sacrificing some speed compared with L1.
• All three are high-speed cache levels and are fundamentally different from secondary storage.
వివరణ:
Question 7
ప్రశ్న 7
What is the main performance purpose of providing cache memory between the CPU and comparatively slower main memory?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Cache keeps selected information close to the CPU so that many accesses can be satisfied without waiting for main memory.
• This reduces average memory-access delay when cache hit rates are useful.
• Cache is therefore a performance mechanism rather than permanent mass storage.
• This reduces average memory-access delay when cache hit rates are useful.
• Cache is therefore a performance mechanism rather than permanent mass storage.
వివరణ:
Question 8
ప్రశ్న 8
Which comparison between CPU registers and cache memory is generally correct?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Registers are extremely small high-speed storage locations directly used by CPU execution circuitry.
• Cache is also very fast but has greater capacity and is normally slower than CPU registers.
• Both registers and ordinary cache are volatile rather than permanent storage.
• Cache is also very fast but has greater capacity and is normally slower than CPU registers.
• Both registers and ordinary cache are volatile rather than permanent storage.
వివరణ:
Question 9
ప్రశ్న 9
Which statement best explains why CPU registers are important for processor performance?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Processor instructions repeatedly require immediate access to operands, addresses and intermediate values.
• Registers provide this information with very low access delay because they are located within the CPU.
• Their capacity is extremely limited, so they complement rather than replace cache, RAM and secondary storage.
• Registers provide this information with very low access delay because they are located within the CPU.
• Their capacity is extremely limited, so they complement rather than replace cache, RAM and secondary storage.
వివరణ:
Question 10
ప్రశ్న 10
A cache has a hit ratio of 90%. What does this mean?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Hit ratio measures the fraction of memory requests for which the requested information is found in cache.
• A 90% hit ratio therefore means roughly 90 out of every 100 relevant accesses are cache hits.
• A higher hit ratio generally reduces the number of accesses that must proceed to slower memory.
• A 90% hit ratio therefore means roughly 90 out of every 100 relevant accesses are cache hits.
• A higher hit ratio generally reduces the number of accesses that must proceed to slower memory.
వివరణ:
Question 11
ప్రశ్న 11
During a memory read operation, which CPU register is associated with holding the address of the memory location that is to be accessed?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• The Memory Address Register holds the address of the memory location involved in a read or write operation.
• The corresponding data being transferred is associated with a data/buffer register rather than the address register.
• The Instruction Register and accumulator have different processor functions.
• The corresponding data being transferred is associated with a data/buffer register rather than the address register.
• The Instruction Register and accumulator have different processor functions.
వివరణ:
Question 12
ప్రశ్న 12
Which CPU register is commonly associated with temporarily holding data being transferred to or from main memory?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• The Memory Data Register, also called a Memory Buffer Register in some descriptions, temporarily holds data moving between the processor and memory.
• The Memory Address Register specifies the location involved in the transfer.
• The Program Counter and Instruction Register are primarily associated with instruction sequencing and current-instruction handling.
• The Memory Address Register specifies the location involved in the transfer.
• The Program Counter and Instruction Register are primarily associated with instruction sequencing and current-instruction handling.
వివరణ:
Question 13
ప్రశ్న 13
In many multicore processors, which cache level is commonly designed as a comparatively large cache shared among multiple processor cores?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• In many modern multicore designs, L3 cache is shared by multiple processor cores.
• L1 caches are commonly closely associated with individual cores, while exact L2 arrangements vary by architecture.
• The important general distinction is that L3 tends to provide larger shared high-speed storage below the smaller private upper cache levels.
• L1 caches are commonly closely associated with individual cores, while exact L2 arrangements vary by architecture.
• The important general distinction is that L3 tends to provide larger shared high-speed storage below the smaller private upper cache levels.
వివరణ:
Question 14
ప్రశ్న 14
Which type of semiconductor memory is commonly used to implement processor cache because it provides high-speed access without requiring the refresh operation associated with DRAM?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Cache memory is commonly implemented using Static RAM because SRAM provides very fast access and does not require periodic refresh while powered.
• DRAM provides much greater density at lower cost and is therefore commonly used for main memory.
• Magnetic and optical technologies are associated with secondary storage rather than CPU cache.
• DRAM provides much greater density at lower cost and is therefore commonly used for main memory.
• Magnetic and optical technologies are associated with secondary storage rather than CPU cache.
వివరణ:
Question 15
ప్రశ్న 15
A processor accesses the same instruction repeatedly inside a program loop. The tendency for recently accessed information to be needed again soon is known as:
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Temporal locality refers to the tendency for recently accessed information to be accessed again in the near future.
• Repeated execution of instructions in a loop is a standard example of this behaviour.
• Cache memory exploits this tendency by retaining recently used information close to the CPU.
• Repeated execution of instructions in a loop is a standard example of this behaviour.
• Cache memory exploits this tendency by retaining recently used information close to the CPU.
వివరణ:
Question 16
ప్రశ్న 16
A program accesses one memory location and is then likely to access nearby locations shortly afterward. This behaviour illustrates:
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Spatial locality describes the tendency for addresses near a recently accessed address to be used soon afterward.
• Sequential instruction execution and array traversal often exhibit this behaviour.
• Cache systems take advantage of spatial locality by transferring blocks containing nearby information.
• Sequential instruction execution and array traversal often exhibit this behaviour.
• Cache systems take advantage of spatial locality by transferring blocks containing nearby information.
వివరణ:
Question 17
ప్రశ్న 17
Which of the following would normally have the greatest immediate effect on memory-access delay when a requested item is not found in L1 cache?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• An L1 cache miss requires the processor to search lower levels of the memory hierarchy.
• Because those levels have longer access times, the request takes longer than an L1 hit.
• This additional delay is one of the major reasons cache hit rate matters to processor performance.
• Because those levels have longer access times, the request takes longer than an L1 hit.
• This additional delay is one of the major reasons cache hit rate matters to processor performance.
వివరణ:
Question 18
ప్రశ్న 18
Assume a cache access takes 2 ns. The cache hit rate is 90%, and on the remaining 10% of accesses an additional 50 ns main-memory penalty is incurred after the cache lookup. What is the average access time under these assumptions?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Every access first incurs the 2 ns cache lookup time.
• The additional average miss cost is 0.10 × 50 ns = 5 ns.
• Therefore the average access time is 2 ns + 5 ns = 7 ns.
• The additional average miss cost is 0.10 × 50 ns = 5 ns.
• Therefore the average access time is 2 ns + 5 ns = 7 ns.
వివరణ:
Question 19
ప్రశ్న 19
Which sequence correctly arranges the following storage levels from generally fastest to slowest access?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Registers provide the fastest storage available directly to CPU execution circuitry.
• Within the cache hierarchy, L1 is generally fastest, followed by L2 and then L3.
• Main memory is slower than these processor cache levels, giving Registers → L1 → L2 → L3 → RAM.
• Within the cache hierarchy, L1 is generally fastest, followed by L2 and then L3.
• Main memory is slower than these processor cache levels, giving Registers → L1 → L2 → L3 → RAM.
వివరణ:
Question 20
ప్రశ్న 20
Consider the following statements:
1. CPU registers have very small capacity but extremely high speed.
2. Cache memory helps reduce the processor's dependence on slower main-memory accesses.
3. A cache hit normally requires accessing main memory before the cached value can be used.
4. Increasing the useful cache-hit ratio can improve average memory-access performance.
Which statements are correct?
1. CPU registers have very small capacity but extremely high speed.
2. Cache memory helps reduce the processor's dependence on slower main-memory accesses.
3. A cache hit normally requires accessing main memory before the cached value can be used.
4. Increasing the useful cache-hit ratio can improve average memory-access performance.
Which statements are correct?
Select an option first. || ముందుగా ఒక సమాధానాన్ని ఎంచుకోండి.
Explanation:
• Statements 1 and 2 correctly describe registers and the performance purpose of cache memory.
• Statement 3 is incorrect because a cache hit means the requested information is already available at that cache level and does not require main memory merely to obtain that item.
• Statement 4 is correct because more requests being served by faster cache can reduce average memory-access time.
• Statement 3 is incorrect because a cache hit means the requested information is already available at that cache level and does not require main memory merely to obtain that item.
• Statement 4 is correct because more requests being served by faster cache can reduce average memory-access time.
వివరణ:
Answer Key సమాధానాల పట్టిక
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Question 1 ప్రశ్న 1Answer: C. L1 cache సమాధానం: C.
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Question 2 ప్రశ్న 2Answer: A. Program Counter సమాధానం: A.
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Question 3 ప్రశ్న 3Answer: D. Instruction Register సమాధానం: D.
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Question 4 ప్రశ్న 4Answer: B. Cache hit సమాధానం: B.
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Question 5 ప్రశ్న 5Answer: B. The required information must be obtained from a lower level of the memory hierarchy. సమాధానం: B.
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Question 6 ప్రశ్న 6Answer: C. L1 is generally the smallest and fastest, while higher-numbered cache levels tend to provide greater capacity with longer access time. సమాధానం: C.
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Question 7 ప్రశ్న 7Answer: A. To reduce the average time required by the processor to access frequently needed data and instructions సమాధానం: A.
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Question 8 ప్రశ్న 8Answer: D. Registers are generally smaller and faster than cache memory. సమాధానం: D.
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Question 9 ప్రశ్న 9Answer: C. They provide extremely fast temporary locations for operands, addresses, instructions and intermediate results required during processing. సమాధానం: C.
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Question 10 ప్రశ్న 10Answer: D. Approximately 90% of the relevant memory requests are satisfied from the cache. సమాధానం: D.
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Question 11 ప్రశ్న 11Answer: B. Memory Address Register సమాధానం: B.
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Question 12 ప్రశ్న 12Answer: A. Memory Data Register సమాధానం: A.
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Question 13 ప్రశ్న 13Answer: D. L3 cache సమాధానం: D.
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Question 14 ప్రశ్న 14Answer: C. SRAM సమాధానం: C.
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Question 15 ప్రశ్న 15Answer: A. Temporal locality సమాధానం: A.
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Question 16 ప్రశ్న 16Answer: B. Spatial locality సమాధానం: B.
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Question 17 ప్రశ్న 17Answer: C. The processor must obtain the information from a lower cache level or main memory, producing additional access delay. సమాధానం: C.
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Question 18 ప్రశ్న 18Answer: A. 7 ns సమాధానం: A.
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Question 19 ప్రశ్న 19Answer: D. Registers → L1 cache → L2 cache → L3 cache → RAM సమాధానం: D.
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Question 20 ప్రశ్న 20Answer: B. 1, 2 and 4 only సమాధానం: B.